White Rabbit nodes are the devices that make up a White Rabbit network. By combining Synchronous Ethernet (SyncE) with Precision Time Protocol (PTP), White Rabbit keeps every connected device aligned to a common clock, even over fiber links spanning many kilometers. Each node measures and compensates for link delays to achieve picosecond-level precision and low jitter. Built on open hardware and compatible with standard Ethernet, White Rabbit nodes are used in many applications from telecommunications to scientific research.

The White Rabbit PTP Core

The White Rabbit PTP Core (WRPC) is an open-source implementation of the White Rabbit protocol, designed to be embedded in an FPGA.

It is FPGA-agnostic, so it can be ported across different vendors and device families, and it is maintained by the White Rabbit Collaboration.
It is the heart of each WR Node, providing complete functionality in a compact, reusable block.
WRPC disciplines the reference clocks and outputs time references (such as a pulse per second and timestamps) that user logic can use directly. This makes it straightforward to add White Rabbit synchronization to timing cards, data acquisition systems, and other custom hardware.

Links to the git repositories can be found at the end of the page.

WRPC Instantiation

Integrating White Rabbit into an HDL design requires three main components: WRPC itself, a set of FPGA/platform-specific modules (such as the PHY, clock buffers and PLLs), and a means of disciplining the reference clock (e.g. DACs driving the oscillators).

Platform/FPGA Specific Modules

The WR core separates platform-dependent FPGA resources from the platform independent core logic. Platform-specific modules provide the PHY, FPGA transceiver and clocking resources required by a target device.
Platform modules are organized by FPGA vendor and device generation or transceiver family.
Supported FPGA families with platform-specific modules are listed below, together with the link to the repository hosting all the modules.
As WRPC is open source, contributions adding new platforms are welcome.

  • Altera Arria II
  • Altera Arria V
  • Altera Arria 10
  • Xilinx Virtex-5
  • Xilinx 6 Series (Spartan-6 and Virtex-6)
  • Xilinx 7 Series (Artix-7, Kintex-7, Virtex-7 and Zynq 7000)
  • Xilinx UltraScale
  • Xilinx UltraScale+

Hardware

Here you can browse some examples of open-source White Rabbit node board designs.

BabyWR

BabyWR is being developed as a cost effective and small pluggable WR node (M.2 form-factor).
BabyWR is designed for low phase noise timing generation. For applications that demand ultimate low phase noise, an external high precision oscillator can be disciplined and used as reference clock.

SPEC-A7

The White Rabbit Node: SPEC-A7 is a PCIe board, designed for deterministic, low-jitter communication in time-critical systems. Paired with the LiteX White Rabbit NIC firmware, it enables sub-nanosecond synchronization and hardware-level packet timestamping (PMT).

CUTE-WR-A7

The Cute-WR project aims to build a self-contained White Rabbit Node implementation on a FPGA Mezzanine Card. The idea is to have a compact, low-cost and common WR node for synchronous DAQ frontends and other applications.

Software and firmware

Below you’ll find links to the open-source firmware, gateware and software for White Rabbit nodes, maintained by the White Rabbit Collaboration.